The present invention relates to technique for testing and manufacturing electronic devices such as semiconductor devices, electric circuit boards and CCD devices.
Recently, in order to increase competitive power of products in a market, it is indispensable to shorten a development term of products. However, since it takes several tens of days from setting of products on a manufacturing line to complete test of electrical characteristics for judging whether products are good or not upon completion of the products, it is late even if a counterplan is considered after reception of the tested results of the electrical characteristics.
In order to solve the above problem, there is a method that in development of products a common process is divided into blocks and electrical test is made in each block, so that its tested result is fed back to the process to establish the process of the block early. A sample for monitoring the block is named a test structure, a short loop monitor or a test element group (TEG). Hereinafter, these are named test structures generically. An example of the test structure is disclosed in xe2x80x9cIntegrated Circuit Manufacturability, IEEE PRESS, pp. 26-29xe2x80x9d.
As technique of specifying a short-circuited position occurring in the test structure, there is the technique of detecting difference in a voltage state on a surface of a wiring pattern by means of irradiation of a charged particle beam such as an electron beam or focused ion beam, that is, the technique of obtaining voltage contrast to detect a position of a defect. An example of the test structure utilizing this technique is disclosed in xe2x80x9cMicroelectronic Test Structures for Rapid Automated Contactless Inline Defect Inspection, IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No. 3, August 1997xe2x80x9d.
However, in the above prior art, it is necessary to irradiate all of test structure patterns in a wafer with a charged particle beam and accordingly a lot of test time is required. Particularly, when defects are few in one wafer, the ratio of normal test structure patterns occupying the wafer is increased that much and the time for testing the normal test structure patterns occupies the most part in spite of the test for detecting unusual portions, so that work efficiency is reduced.
More particularly, in the prior art, the test structure for specifying a short-circuited position efficiently is not studied sufficiently. Accordingly, a considerable time is taken for test and analysis and the time required to feed the result thereof back to a manufacturing line is delayed, so that the yield cannot be improved effectively. Particularly, the test structure intended to effectively use the voltage contrast method has not been studied sufficiently.
Further, in the prior art, short circuit and open circuit cannot be discriminated from each other efficiently and a considerable time is taken for test and analysis thereof in the same manner as above, so that the time required to feed the result thereof back to a manufacturing line is delayed and the yield cannot improved effectively.
It is an object of the present invention to improve the efficiency of the test using the test structure to thereby improve the yield.
In order to attain the above object, according to the present invention, the manufacturing method of an electronic device for performing test using a first lead wire disposed on an insulating layer formed in a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and managing the electronic device using the tested results to be manufactured, comprises a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
Further, according to the present invention, the manufacturing method of an electronic device for performing test using a first lead wire disposed on an insulating layer formed in a p-type silicon substrate and a second lead wire electrically connected through an n-channel formed in the p-type silicon substrate and disposed on the insulating layer and managing the electronic device using the tested results to be manufactured, performs test as to whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the p-type silicon substrate.